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Intellectual Ventures控告Toshiba之NAND快閃記憶體等產品侵犯其10項專利

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科技產業資訊室 (iKnow) - SYL 發表於 2013年3月28日

2013年3月20日,知名專利授權公司高智發明(Intellectual Ventures)之子公司Intellectual Ventures I LLC 與Intellectual Ventures II LLC(下稱IV),向美國德拉瓦州聯邦地院提起專利侵權告訴,控告日本跨國電子大廠與半導體記憶體製造商Toshiba Corporation及其美國分公司Toshiba America, Inc.、Toshiba America Electronic Components, Inc.與Toshiba America Information Systems, Inc. (下稱Toshiba)等,其所製造販售之NAND快閃記憶體(NAND flash memory)產品及內含前述記憶體的消費電子產品、內含USB主端控制晶片(USB host controller)之電子產品、具備ETM(Embedded Trace Macrocell)技術之ARM微處理器(ARM-based controller)產品及內含前述微處理器的電子產品、以及應用序列ATA(serial ATA, SATA)標準之硬碟機產品及內含前述硬碟機的電子產品等,侵犯分別由原告兩家IV子公司所擁有的10項專利權利。

在本案訴狀中,IV控告Toshiba之NAND記憶體相關產品侵犯US 5,500,819(’819專利)、US 5,568,431(’431專利)、US 5,600,606(’ 606專利)、US 5,687,132(’ 132專利)、US 5,701,270(’ 270專利)、US 5,829,016(’ 016專利)與 US 6,058,045(’ 045專利)等7項專利權利。另外IV亦控告Toshiba之內含USB主端控制晶片產品、ARM微處理器相關產品與SATA硬碟機相關產品,分別侵犯了US 5,938,742(’ 742專利)、US 7,836,371(’371專利)與US 6,618,788(’ 788專利)等3項專利權利。

本案10項系爭發明專利之簡要內容如下:

’819專利名稱為「用來在一記憶體系統中增進分頁存取與區塊轉移的電路、系統與方法(Circuits, systems and methods for improving page accesses and block transfers in a memory system)」,於1996年3月19日核發;

’431專利名稱為「記憶體架構與裝置,及其使用系統與方法(Memory architecture and devices, systems and methods utilizing the same)」,於1996年10月22日核發;

’ 606專利名稱為「使用非多工定址之低針腳數記憶體裝置及其使用系統與方法(Low pin count - wide memory devices using non-multiplexed addressing and systems and methods using the same)」,於1997年2月4日核發;

’ 132專利名稱為「多排記憶體架構及其使用系統與方法(Multiple-bank memory architecture and systems and methods using the same)」,於1997年11月11日核發;

’ 270專利名稱為「具備跨排替換儲存單元功能之單晶片控制器記憶體裝置以及適合其實施的記憶體架構與方法(Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same)」,於1997年12月23日核發;

’ 016專利名稱為「具備多工輸入輸出埠之記憶體系統及其使用系統與方法(Memory system with multiplexed input-output port and systems and methods using the same)」,於1998年10月27日核發,以上6項專利之原始權利人均為Cirrus Logic, Inc.;

’ 742專利名稱為「用於配置一智慧型低功率序列匯流排的方法(Method for configuring an intelligent low power serial bus)」,於1999年8月17日核發,原始權利人為General Magic, Inc.;

’ 045專利名稱為「序列快閃記憶體(Serial flash memory)」,於2000年5月2日核發,原始權利人為Azalea Microelectronics;

’ 788名稱為「透過一封包介面進行ATA標準裝置控制(ATA device control via a packet-based interface)」,於2003年9月9日核發,原始權利人為Cypress Semiconductor, Inc.;

’371專利名稱為「晶載服務處理器(On-chip service processor)」,於2010年11月16日核發,發明人與原始權利人為Bulent Dervisoglu等3人。

IV之首席訴訟顧問(Chief Litigation Counsel)Melissa Finocchio在其公開聲明稿中指出,包括本案系爭專利在內的IV專利組合已授權給多家國際級半導體記憶體製造商,如三星(Samsung)、美光(Micron)、我國的南亞科技等,而由於IV與Toshiba協商授權條件未能達成共識,是故IV選擇以興訟方式來主張權利。(1412字;表2)

表一、系爭發明專利之請求項解析

US 5,500,819? 請求項1 US 5,568,431? 請求項1
1. A memory (Fig.2 - 200) comprising:
一項記憶體,包括
1. A memory device (Fig.2 - 200) comprising:
一項記憶裝置,包括
an array (Fig.2 - 201) of rows and columns of volatile memory cells (Fig.2 - 202);
由依電性儲存單元所構成列與行的陣列
a plurality of arrays (Fig.2 - 202) of memory cells (Fig.2 - 203);
複數之儲存單元陣列
addressing circuitry for providing access to selected ones of said memory cells;
定址電路,其用來提供存取到前述儲存單元中被擇定者
a plurality of registers (Fig.2 - 211), each of said registers for exchanging parallel bits of data with a corresponding one of said arrays; and
複數暫存器,每個前述暫存器用來與前述陣列中一相對應者交換平行位元資料
master read/write circuitry for reading and writing data into said selected ones of said cells;
主讀寫電路,其用來讀取與寫入資料到前述儲存單元中被擇定者
data transfer circuitry (Fig.2 - 208) for transferring parallel bits of data from any selected one of said arrays through the corresponding said register to any other selected one of said arrays through the corresponding said register.
資料轉移電路,其用來經由相對應之前述暫存器從任一被擇定之前述陣列,轉移平行位元資料,經由相對應之前述暫存器到任何另一個被擇定之前述陣列
first slave circuitry for storing data for exchange with said master read/write circuitry;
第一從屬電路,其用來儲存與前述主讀寫電路進行交換之資料
pclass_13_A111b.gif
second slave circuitry for storing data for exchange with said master read/write circuitry; and
第二從屬電路,其用來儲存與前述主讀寫電路進行交換之資料
control circuitry for controlling exchange of data between said master read/write circuitry and said first and second slave circuitry, said control circuitry operable during a move operation to:
控制電路,其用來控制前述主讀寫電路與前述第一和第二從屬電路間的資料交換,前述控制電路在一移動作業間可運作來:
control sensing by said master read/write circuitry of data from a said row in said array selected by said addressing circuitry;
控制前述主讀寫電路感測來自被前述定址電路所擇定之一前述列的資料
control transfer of said data from said master read/write circuitry to a selected one of said first and second slave circuitry; and
控制從前述主讀寫電路轉移前述資料到前述第一和第二從屬電路中被擇定者
control writing of said data through said master read/write circuitry to a second said row in said array selected by said addressing circuitry.
控制透過前述主讀寫電路寫入前述資料到在前述陣列中被前述定址電路所擇定之第二個前述列
pclass_13_A111a.gif
US 5,600,606 請求項1 US 5,687,132 請求項1
1. A method of operating a memory device (Fig.2 - 200) including a plurality of multiplexed data/address input/output terminals (Fig.2 – 220, 230 & 240), an array of memory cells (Fig.2 - 201), and circuitry for accessing selected ones of the memory cells in response to received row and column address bits, the method comprising the steps of:
一項操作記憶裝置的方法,該記憶裝置包含複數個多工資料/定址與輸入/輸出終端、一儲存單元陣列、與回應所接收列與行位址位元來存取被選擇儲存單元之電路,該方法包括以下步驟
1. A memory (Fig.2A - 20) comprising:
一項記憶體,包括
substantially simultaneously inputting said row address bit and column address bit during an address cycle, at least one of said row and column address bits input through a selected one of the multiplexed terminals; and
實質並同時在一定址週期中輸入前述列位址位元與行位址位元,至少一個前述列與行位址位元是經由被選擇之其中一個多工終端來輸入
a first plurality of columns of memory cells (Fig.2A – 200a) each including at least one conductive bitline (Fig.2A - 202);
一第一群之複數儲存單元行,各自包括至少一個導電位元線
accessing ones of the memory cells addressed by the row and column bits through selected ones of the multiplexed terminals during a data access cycle.
存取在儲存單元中、在資料存取週期中、經由被選擇其中一個多工終端、而依列與行位元所定址者
a second plurality of columns of memory cells (Fig.2A – 200b) each including at least one conductive bitline; and
一第二群之複數儲存單元行,各自包括至少一個導電位元線
pclass_13_A111c.gif
a plurality of gates (Fig.2A - 203) organized in independently controlled groups for selectively coupling said bitlines of a selected group of said first plurality of columns with a group of said bitlines of said second plurality of columns for transferring a at least one bit of data from a selected cell of said first plurality of columns of cells to a selected cell of said second plurality of columns of cells.
複數閘,其被組織在獨立被控制的群組中,用來選擇性耦接前述第一群複數行中被選擇群組之前述位元線與前述第二群複數行一組前述位元線,以從前述第一群複數儲存單元行中一被選擇之單元,轉移一至少一位元的資料到前述第二群複數儲存單元行中一被選擇之單元
pclass_13_A111d.gif
US 5,701,270 請求項1 US 5,829,016 請求項1
1. A memory subsystem (Fig.3 - 300) comprising:
一項記憶體子系統,包括
1. A memory (Fig.2 - 200) comprising:
一項記憶體,包括
processing circuitry;
處理電路
a plurality of input/output terminals (Fig.2 - 220) multiplexed by cycle for exchanging data bits during a data access cycle and receiving addresses command opcodes and control bits during a command and control cycle;
複數輸入輸出終端,在一資料存取週期中多工處理交換資料位元之週期,並在一命令與控制週期中接收位址指令作業碼與控制位元
first and second banks of memory, each said bank including a predetermined number of primary memory cells and a predetermined number of redundant memory cells;
第一與第二記憶體組,個別前述記憶體組包括一預設數量的主要儲存單元與一預設數量的冗餘記憶單元
an array (Fig.2 - 201) of memory cells;
一儲存單元陣列
a primary address bus (Fig.3 - 202) for allowing said processing circuitry to address at least one of said primary memory cells, said at least one primary memory cell residing in a primary cell memory space; and
一主要位址匯流排,其用來讓前述處理電路就至少一個前述主要儲存單元進行定址,前述至少一個主要儲存單元位於一主要儲存單元記憶體空間
data input/output circuitry for transferring data between said input/output terminals and said array of memory cells during said data access cycle; and
資料輸入輸出電路,用來在前述輸入輸出終端與前述儲存單元陣列間,在前述資料存取週期中轉移資料
a redundancy bus (Fig.3 - 301) for allowing said processing circuitry to address at least one of said redundancy cells, said at least one redundancy cell residing in a redundacy cell memory space separate from said primary cell memory space.
一冗餘匯流排,其用來讓前述處理電路就至少一個前述冗餘儲存單元進行定址,前述至少一個冗餘儲存單元位於一冗餘儲存單元記憶體空間,其與前述主要儲存單元記憶體空間分隔
control circuitry (Fig.2 - 216) for controlling operations of said memory in response to command opcodes and control bits received at said input/output terminals during said command and control cycle.
控制電路,用來回應前述輸入輸出終端在前述命令與控制週期中所接收之指令作業碼與控制位元,控制前述記憶體運作
pclass_13_A111e.gif
pclass_13_A111f.gif
US 5,938,742 請求項1 US 6,058,045 請求項1
1. A method for detecting disconnection of a peripheral device from a bus comprising:
一項用來偵測一周邊裝置從一匯流排拆接之方法,包括
1. An array (Fig.4 - 400) of flash memory cells (Fig.4 - 402) comprising:
一項快閃記憶體儲存單元陣列,包括
generation of an interrupt signal on said bus to a host computer for said bus from one peripheral device on said bus upon disconnection of another peripheral device on said bus wherein said one peripheral device is upstream on said bus from said another peripheral device; and
從在前述匯流排上之一周邊裝置、當在前述匯流排上之另一周邊裝置有拆接狀況時,在前述匯流排上產生一中斷訊號到主電腦,其中前述周邊裝置較另一周邊裝置位於前述匯流排上更上游的位置
a plurality of columns of serially connected flash memory cells, each memory cell having a gate terminal;
複數串聯快閃記憶體儲存單元行,每個記憶體儲存單元具備一閘終端
a plurality of bit lines (Fig.4 – BL0-BL15) respectively coupled to drain side of said plurality of columns of memory cells via a respective plurality of bit line select transistors (Fig.4 - 404), said plurality of bit line select transistors having gate terminals coupled to a bit line select control line (Fig.4 - BSL);
複數位元線,個別透過個別位元線選擇電晶體耦接前述記憶體儲存單元行的汲極,前述複數位元線選擇電晶體具備耦接於一位元線選擇控制線之閘終端
a plurality of word lines (Fig.4 – WL0-WL15), each one coupling to a gate terminal of one memory cell in each of said plurality of columns to from rows of memory cells with common gate terminals; and
複數字元線,個別耦接於在每個前述複數儲存單元行上一個記憶體儲存單元的閘終端,以形成具備共同閘終端的記憶體儲存單元列
performance of an interrupt poll sequence by said host computer in response to said interrupt signal wherein said interrupt poll sequence detects disconnection of said another peripheral device.
由前述主電腦執行一中斷輪詢序列,來回應前述中斷訊號,而前述中斷輪詢序列偵測前述另一周邊裝置的切接
a plurality of source select transistors (Fig.4 - 406) respectively coupling a source side of said plurality of columns of memory cells to a logic low voltage, and having gate terminals coupled to a source select control line,
複數來源選擇電晶體,個別將前述複數記憶體儲存單元行之源極耦接於資邏輯低電壓,並具備被耦接於來源選擇控制線的閘終端
wherein, during programming:
在記憶體進行配置時
a logic high voltage is applied to said bit line select control line to turn on bit line select transistors,
一邏輯高電壓被供到前述位元線選擇控制線上以開啟位元線選擇電晶體
pclass_13_A111g.gif
a logic low voltage is applied to source select control line to turn off source select transistors;
一邏輯低電壓被供到來源選擇控制線上來關閉來源選擇電晶體
a logic low voltage is applied to a selected bit line while a logic high voltage is applied to unselected bit lines, and
一邏輯低電壓被供到一受選擇之位元線上,當邏輯高電壓被供到未受選擇之位元線上
a logic high voltage is applied to unselected word lines, while a boosted positive voltage is applied to a selected word line.
一邏輯高電壓被供到未受選擇之字元線上,當一被促成的正電壓被供到一受選擇之字元線上
pclass_13_A111h.gif
US 6,618,788 請求項1 US 7,836,371 請求項1
1. A method of controlling an ATA device (Fig.7 - 186) using packet-based communication between a host (Fig.7 - 130) and a packet-to-ATA bridge, the method comprising at the host:
一項使用主機與封包到ATA橋接器間所進行封包通訊來控制ATA標準裝置的方法,該方法在主機端包括
1. An integrated circuit comprising:
一項積體電路,包括
formatting the ATA register accesses necessary to execute a given ATA register-delivered transaction into a command block; and
將必須用於執行一被交付之ATA暫存器遞送交易的ATA暫存器存取,格式化程一命令塊
one or more logic blocks to generate one or more system-operation signals at one or more system-operation clock rates; and
一或多個邏輯塊,用來以一或多個系統運作時鐘率、產生一或多個系統運作訊號
transmitting the command block to the packet-to-ATA bridge in a packet format,
以一封包格式傳送前述命令塊到前述封包到ATA橋接器
a service processor unit (Fig.2 - 101), said service processor unit comprising:
一服務處理器單元,前述服務處理器單元包括
and at the packet-to-ATA bridge:
在封包到ATA橋接器端則包括
a control unit (Fig.2 - 211);
一控制單元
parsing the command block into a sequence of ATA operations necessary to execute the given ATA register-delivered transaction;
將前述命令塊剖析成,一必須用於執行一被交付之ATA暫存器遞送交易的ATA作業序列
a buffer memory (Fig.2 - 218); and
一緩衝記憶體
communicating with an ATA device attached to the bridge via an ATA interface to execute the sequence of ATA operations on the ATA device; and
透過一ATA介面與附接於前述橋接器之一ATA裝置進行通訊,以在前述ATA裝置上執行前述ATA作業序列
a multiplicity of selectable probes,
多重可選擇之探針
when the given ATA register-delivered transaction requests the values for one or more registers on the ATA device, returning the register values to the host in packet format.
當被交付之ATA暫存器遞送交易要求在ATA裝置上一或多個暫存器之數值,以封包格式回覆暫存器數值至主機
wherein said service processor unit is adapted to perform capture and analysis of said system operation signals during normal system operation through said selectable probes.
前述服務處理器單元被調整來,透過前述可選擇之探針,在正常系統運作時執行擷取與分析前述系統運作訊號之功能
pclass_13_A111i.gif
pclass_13_A111j.gif

Source: 科技政策研究與資訊中心—科技產業資訊室整理,2013/03

表二、專利訴訟案件基本資料:IV控告Toshiba

訴訟名稱 Intellectual Ventures I LLC et al v. Toshiba Corporation et al
提告日期 2013年3月20日
原告 Intellectual Ventures I LLC
Intellectual Ventures II LLC
被告 Toshiba Corporation
Toshiba America Inc.
Toshiba America Electronic Components Inc.
Toshiba America Information Systems Inc.
案號 1:13-cv-00453-UNA
訴訟法院 the U.S. District Court for the District of Delaware
系爭專利 US 5,500,819
US 5,568,431
US 5,600,606
US 5,687,132
US 5,701,270
US 5,829,016
US 5,938,742
US 6,058,045
US 6,618,788
US 7,836,371
系爭產品 Toshiba之NAND快閃記憶體(NAND flash memory)產品,及內含NAND快閃記憶體的電子產品,如:
https://www.toshiba.com/taec/Catalog/Family.do?familyid=7&subfamilyid=900114http://storage.toshiba.com/storagesolutions/pc-notebook/mq01abdh-series (最後瀏覽日:2013/03/28);
Toshiba之內含USB主端控制晶片(USB host controller)的電子產品;
Toshiba之具有ETM技術的ARM微處理器(ARM-based controller with ETM)產品,及內含前述微處理器的電子產品,如:
http://www.toshiba.com/taec/Catalog/Family.do?familyid=14 (最後瀏覽日:2013/03/28);
Toshiba之應用序列ATA(serial ATA, SATA)標準的硬碟機產品,及內含前述硬碟機的電子產品,如:
http://storage.toshiba.com/storagesolutions/pc-notebook/mq01abdh-series# (最後瀏覽日:2013/03/28)
訴狀下載 download.gif

Source: 科技政策研究與資訊中心—科技產業資訊室整理,2013/03


 
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