| US 6,920,316 請求項1 |
US 5,825,640 請求項1 |
1. A regulation circuit (Fig.1 - 30) having an input coupled to a power supply, said power supply (Fig.1 - 310) for producing a source voltage, and a first output coupled to a first circuit load, said regulation circuit comprising:
一項整流電路，其具備連接電力供應的輸入端而前述電力供應產生源極電壓，並具備第一個輸出端與第一個電路負載連接，前述整流電路包括 |
1. A charge pump (Fig.3 - 26), comprising:
一項電荷幫浦，包括 |
an input capacitor (Fig.1 - 109), coupled to said input and ground, for reducing the magnitude of a voltage change at said first output;
輸入電容器，連接輸入端與地面，用以降低前述輸出端的電壓變化量 |
a first current conduction path (Fig.3 – 36 & 37) responsive to a first input pulse for supplying a pump current to an output (Fig.3 - 31) of the charge pump; and
第一個電流傳導通路，回應第一個輸入電流脈衝，用以供應幫浦電流至電荷幫浦的輸出端 |
and at least a first voltage regulator (Fig.1 - 112), coupled to said input capacitor, for producing a predetermined voltage at said first load;
第一個穩壓器，連接前述輸入電容器，用以在前述第一個負載上產生預設的電壓 |
whereby said regulation circuit and said first circuit load are incorporated in a single integrated circuit;
而前述整流電路與前述第一個電路負載被整合在單一積體電路上 |
a charge circuit (Fig.3 – 32 & 35) coupled to a first node (Fig.3 – 38 & 39) of the first current conduction path where the charge circuit is disabled during a first transition of the first input pulse and enabled during a second transition of the first input pulse to alter a charge on the first node.
與第一個電流傳導通路之第一個節點連接之電荷電路，其在第一個輸入電流脈衝的第一次轉移時不發揮作用，而在第一個輸入電流脈衝的第二次轉移時發揮作用，改變第一個節點的電荷 |
wherein said input capacitor is a thin oxide N-channel transistor.
前述輸入電容器為薄氧化層N型通道電晶體 |
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| US 5,943,274 請求項1 |
US 7,927,927 請求項1 |
1. An apparatus for use as an output stage of a memory device, the apparatus comprising:
一項用作記憶體設備之輸出的裝置，包括 |
1. A method for making a packaged semiconductor device comprising:
一項製作經封裝之半導體裝置的方法，包括 |
a timing circuit (Fig.2 - 104);
定時電路 |
providing an interconnect substrate (Fig.1 - 11) having a plurality of substantially identical package sites (Fig.1- 13, 14, 16, 21, 22 & 23) arranged in an array, the plurality of sites being separated by a singulation space (Fig.1 -17) and the interconnect substrate being a ceramic substrate or a rigid printed circuit board substrate;
提供多層連線基板，其具備排成一列之複數的相同封裝處理區域，複數區域為去框之間隔所區劃，而多層連線基板為陶瓷電路板或硬式印刷電路板基板 |
a differential amplifier (Fig.2 - 100) responsive to the timing circuit;
回應定時電路之差動放大器 |
mounting and interconnecting a semiconductor device within each site;
在每個區域粘著並互連出半導體裝置 |
an impedance control circuit (Fig.2 – 108 & 110);
阻抗控制電路 |
forming a cavity containing the plurality of substantially identical package sites;
形成裝載複數之相同封裝處理區域的空腔 |
a level converter (Fig. - 102) responsive to the differential amplifier and the impedance control circuit; and
回應差動放大器與阻抗控制電路之電壓位準轉換器 |
and overmolding a single and continuous encapsulant over each semiconductor device, the plurality of sites, and the singulation space, wherein overmolding produces a top surface of the continuous encapsulant which has a surface deviation of less than 0.13 millimeters across the top surface of the continuous encapsulant.
在每個半導體裝置、複數處理區域與去框間隔上覆蓋成型單一而無間斷的封裝物，覆蓋成型的動作產製出無間斷封裝物的上表面，而無間斷封裝物上表面之表面厚度的變異量小於0.13毫米 |
a clock-free latch (Fig.2 - 106) responsive to the level converter.
回應電壓位準轉換器之無時脈訊號閂鎖器 |
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| US 5,467,455 請求項1 |
1. A data processing system having a communication device (Fig.1 – 10 & 12), the communication device being an integrated circuit having a plurality of external pins, the plurality of external pins being coupled to receive data from external to the communication device and transmit data external to the communication device, the communication device comprising:
一項具備通訊裝置的資料處理系統，通訊裝置為具備複數外部接點之積體電路，複數外部接點可從外部接收資料至通訊裝置並傳送外部資料到通訊裝置，該通訊裝置包括 |
circuitry for signal termination (Fig.1 - 14) having a plurality of first input/output terminals (Fig.1 - 13) coupled to the plurality of external pins via a plurality of data lines,
訊號終結之電路，具備透過複數資料線連接複數外部接點之複數個第一輸入/輸出端子 |
the circuitry for signal termination having a second input/output terminal (Fig.1 – 22 & 24) for providing data to or receiving data from internal to the communication device,
訊號終結之電路具備一個第二輸入/輸出端子，用以從內部提供或接收資料到通訊裝置 |
the circuitry for signal termination having an input for receiving an enable signal from either internal or external to the communication device and having a termination component,
訊號終結之電路具備用以接收來自通訊裝置內部或外部之致能訊號的輸入端，並具備一終結元件 |
the enable signal allowing the circuitry for signal termination to couple the termination component to the plurality of external pins when the enable signal is asserted and decoupling the termination component from the plurality of external pins when the enable signal is deasserted.
當致能訊號被設置時，致能訊號讓訊號終結之電板將終結元件與複數外部接點連接，而當致能訊號被取消設置時，將終結元件與複數外部接點之連接中斷 |
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